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ELECTRONIC DESIGN AUTOMATION - EDA

Machine Learning-Assisted Run-Time Power and Thermal Estimation in High-Performance Computing Processors

azienda Tesi esterna in azienda    estero Tesi all'estero


Parole chiave C, DEEP LEARNING, DESIGN SPACE EXPLORATION, EMBEDDED SYSTEMS, ENERGY EFFICIENCY, FIRMWARE, HARDWARE AND SOFTWARE, HARDWARE DESIGN, HIGH PERFORMANCE PROCESSORS, LOW POWER, MACHINE LEARNING, POWER, POWER ESTIMATION, PPACT, PROCESSORS, THERMAL, THERMAL MODEL

Riferimenti DANIELE JAHIER PAGLIARI

Riferimenti esterni Yukai Chen (IMEC)

Gruppi di ricerca DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA, ELECTRONIC DESIGN AUTOMATION - EDA, GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA

Tipo tesi EXPERIMENTAL, HARDWARE, SOFTWARE DEVELOPMENT

Descrizione This thesis project addresses a critical challenge in modern computing: run-time power and thermal estimation in high-performance processors empowered by machine learning techniques. This master thesis opportunity, within IMEC's System and Technology Co-optimization (STCO) program, aims to pioneer future technology scaling by optimizing Power, Performance, Area, Cost, and Temperature (PPACT).

The candidate's primary task will be to develop methodologies for run-time power and thermal estimation in high-performance computing processors. Drawing inspiration from recent advancements in machine learning, the candidate will design and implement innovative techniques for accurate and efficient estimation of power and thermal dynamics during run-time[1]. Furthermore, the candidate will explore the integration of machine learning or deep learning techniques into the power and thermal estimation process, building upon the success of frameworks like APOLLO[2]. The thesis research will encompass both dynamic and static power estimation, enabling comprehensive power breakdown analysis crucial for optimizing energy-efficient designs.

In addition to algorithmic development, the candidate will implement your methodologies in real-world scenarios and conduct evaluations using advanced technology nodes and industry-standard benchmarks. This hands-on experience will provide valuable insights into the intricacies of power and thermal management in high-performance computing processors.

The candidate will collaborate closely with the IMEC's team of system architects and PPACT researchers, ensuring alignment with future technology trends and research goals. This collaborative environment will support the candidate in making significant contributions to the field of run-time power and thermal estimation for high-performance computing processors in advanced technology and packages augmented by machine learning.

Type of work: This role provides a balance of theoretical study and hands-on experience, with 20% dedicated to literature study and 80% to hands-on methodology development and RTL-level simulation.
Duration: 6+ months
Link: https://www.imec-int.com/en/work-at-imec/job-opportunities/machine-learning-assisted-run-time-power-and-thermal-estimation-high

References:
[1] Jahier Pagliari, D., Peluso, V., Chen, Y., Calimera, A., Macii, E. and Poncino, M., 2018, March. All-digital embedded meters for on-line power estimation. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 737-742). IEEE.
[2] Xie, Z., Xu, X., Walker, M., Knebel, J., Palaniswamy, K., Hebert, N., Hu, J., Yang, H., Chen, Y. and Das, S., 2021, October. APOLLO: An automated power modeling framework for runtime power introspection in high-volume commercial microprocessors. In MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 1-14).

Vedi anche  https://www.imec-int.com/en/work-at-imec/job-opportunities/machine-learning-assisted-run-time-power-and-thermal-estimation-high

Conoscenze richieste We seek candidates with a background in Electronic/Computer Engineering, possessing a strong understanding of Computer Architecture and Microarchitecture/ISA. Familiarity with classic machine learning methods is preferred. Proficiency in programming languages such as C, Python, SystemVerilog/VHDL, and RTL simulation is necessary.

Note Thesis carried out at the IMEC research center in Leuven, Belgium, under the supervision of Dr. Francky Catthoor, Dr. Yukai Chen, and Dr. Dwaipayan Biswas. The candidate will be financially supported by IMEC for the travel (around 800/1000 Euro per month, not considering potential scholarships).


Scadenza validita proposta 19/04/2025      PROPONI LA TUA CANDIDATURA




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