Floor planning for FPGAs
Riferimenti LUCIANO LAVAGNO
Riferimenti esterni Prof. Jordi Cortadella, Universitat Politecnica de catalunya
Gruppi di ricerca microelettronica
Tipo tesi RESEARCH
Descrizione The goal of the thesis is to implement a floor planner for FPGAs, using a graph partitioning algorithm, to be used during High Level Synthesis.
It receives as input an Llvm file representing the graph of the instructions to be floorplanned, i.e. placed preliminarily on the FPGA, and then scheduled later. Each instruction has a resource estimate (LUT, FF, DSP, BRAM)
It produces as output an estimated location for each instruction on the FPGA.
Conoscenze richieste Placement and routing for FPGAs
Linear and non-linear optimization
Scadenza validita proposta 20/09/2022 PROPONI LA TUA CANDIDATURA