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Hardware-based Machine Learning for Event-Based sEMG-based Gesture Recognition

keywords EDGE COMPUTING, FPGA, INTERNET OF THINGS (IOT), MACHINE LEARNING, SURFACE ELECTROMYOGRAPHY (SEMG), WEARABLE DEVICES

Reference persons DANILO DEMARCHI

External reference persons Paolo Motto Ros (paolo.mottoros@polito.it)

Research Groups MiNES (Micro&Nano Electronic Systems)

Thesis type EXPERIMENTAL

Description Augmenting Internet-of-Things (IoT) and wearable devices with smart functionalities, e.g. based on machine learning techniques, has become nowadays a hot topic: in case of Wireless Body Area network (WBAN) sensors that means not to just continuously acquire and stream raw, low-level, data, but to identify specific high-level patterns, eventually predicting the user?s behavior or (generically speaking) her/his health conditions, and transmit, whenever needed, synthetic information only. Designing the machine learning algorithm is thus just the first step: in order to have an efficient and effective implementation, the underlying hardware platform has to be taken into account, and eventually re/co-designed, aiming at improving the trade-off among the needed hardware resources, power consumption, and computational performance.
Major aim of this thesis is to study the feasibility, and develop a proof-of-concept implementation, of a FPGA-based accelerator for gesture recognition, to be interfaced with a multi-channel event-based surface ElectroMyoGraphy (sEMG) acquisition system (already developed and tested) and integrated in a wearable wireless embedded system. Starting from the investigation of previous works on this sEMG acquisition approach and the already developed software-based machine learning models, through the development and the validation of the digital core deployed on a small, low-power, FPGA, the final goal is to replace and improve, in the actual wearable device, the current software-based gesture recognition system with a more efficient hardware-based one.

Required skills FPGA design and development; HDL (VHDL or Verilog) programming; PCB design


Deadline 16/01/2023      PROPONI LA TUA CANDIDATURA




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