| KEYWORD |
Study of machine learning techniques to improve timing prediction in digital circuits
keywords ASIC DESIGN, MACHINE LEARNING, TIMING CLOSURE
Reference persons MARIO ROBERTO CASU, LUCIANO LAVAGNO
Research Groups microelettronica
Thesis type RESEARCH THESIS WITH A COMPANY
Description Timing prediction, at different stages of ASIC design and implementation, is a key component that can improve final design QoR. However, the timing characteristics of the post-layout netlists usually do not only depend on the gate delays belonging to the synthesized paths but even from the network topology, the number of metal layers available for routing, the clock tree generated during place and route, etc… . For this reason, recently, there is a strong research activity on how to implement timing prediction algorithms using ML and DL techniques.
The first part of this thesis will be to perform an analysis of state of the art ML/DL algorithms applied to EDA. The second part would be to apply them on timing prediction problem given a dataset of netlists.
Required skills Basic knowledge in ML/DL. Good knowledge of python programming. Basic knowledge of TCL scripting. Good knowledge of FPGA design and implementation flow. Knowledge of graph theory is a plus. Knowledge of DL framework like Tensorflow and Pytorch is a plus.
Notes Expected learning outcome:
- Knowledge of ASIC backend tools;
- Knowledge of state of the art ML/DL techniques;
- Knowledge of one of the main framework (Tensorflow/Pytorch) used for DNN development;
Deadline 02/03/2023
PROPONI LA TUA CANDIDATURA