| KEYWORD |
Control logic for low power DC-DC converter and Battery Charger for wearable vital signals monitoring applications
Thesis in external company
keywords BATTERY, DIGITAL DESIGN, INTEGRATED CIRCUIT DESIGN, POWER ELECTRONICS
Reference persons FRANCESCO MUSOLINO
External reference persons La tesi sarà supportata dal team di ingegneri di Analog Devices/Maxim Integrated.
Research Groups Microelectronics
Thesis type DESIGN AND SIMULATIONS
Description The student will be guided in the knowledge and analysis of the operating principles of DC/DC converters and Linear Chargers for supplying power to wearable integrated electronic circuits, in exploring the definition of their analog/digital partitions and in the development of the required logic control laws through FSMs specifically dedicated to manage the operation of analog blocks. Moreover, the student will be guided to understand the sequences of system turn on/off that occur after fault conditions and critical events (UVLO, OVLO, thermal faults, …) generated asynchronously by the analog sections of the system and that are routed out of the chip through serial interfaces (I2C, SPI, I3C, ...) and GPIOs.
In this work, the student will be asked to analyse and optimize RTL building blocks like the sequencer, debouncer, counters, FSMs, clock dividers, external memory controllers and serial communication protocols. At the same time, the student will be involved in the digital design flow, RTL with DFT, logic synthesis, timing analysis, modeling and simulation in UVM environment, ATPG and on the supervision of the digital layout. The main goal of the work is the minimization of the power consumption of the chip by adopting specific architectural solutions (ON/OFF islands, clock gating, …).
Required competences for this work include a basic knowledge of the BCD technology, of Verilog/System Verilog, of DFT concepts, logic synthesis, timing analysis, and the use of simulation softwares.
Required skills Required competences for this work include switching power converters, hardware description languages like Verilog/System Verilog, logic synthesis and timing analysis of digital circuits, and the use of simulation softwares.
Notes The thesis will be carried out in the Analog Devices/Maxim Integrated located in Milan (or Catania). Reimbursement of expenses will be provided.
Deadline 30/06/2022
PROPONI LA TUA CANDIDATURA