| KEYWORD |
Study and development of fault tolerance mitigation methods for TPU architectures
keywords FAULT INJECTION, FAULT TOLERANCE, FPGA ACCELERATION, NEURAL NETWORKS, TPU
Reference persons LUCA STERPONE
External reference persons Eleonora Vacca
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type APPLIED RESEARCH
Description The activity of the present thesis will be devoted to the development of new design methodologies for reprogrammable devices such as FPGA, dedicated to the Tensor Processing Unit (TPU). TPUs are recently extremely interesting not only for High Performance Computing (HPC) but also for automotive and aerospace applications where high levels of dependability and fault tolerance are demanded. The student will extend an available fault injection system on Xilinx FPGAs, verify the robustness of a set of typical benchmark applications within the automotive field, finally the student will have the possibility to develop new mitigation solutions versus transient errors.
Required skills good VHDL knowledge, basic Python experience and interest on embedded hardware systems design techniques.
Deadline 24/07/2022
PROPONI LA TUA CANDIDATURA