| KEYWORD |
Study and development of new TPU architectures for High Performance Computing applications
keywords FAULT INJECTION, FAULT TOLERANCE, FPGA ACCELERATION, NEURAL NETWORKS, TPU
Reference persons LUCA STERPONE
External reference persons Eleonora Vacca
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type APPLIED RESEARCH
Description The activity of the present thesis is focused on the extension of the Instruction Set Architecture (ISA) of a TPU model and of a design of new TPU architecture focused on the optimization of HPC applications. The architecture will be developed on state-of-the-art reconfigurable FPGAs such as Xilinx Ultrascale+ family and it should be devoted to autonomous driving applications. The present thesis is performed in collaboration with the Silk-Faw automotive company. In the framework of the present thesis, it could be possible to spend a study period within Silk-Faw laboratories.
Required skills good VHDL knowledge, basic Python experience and interest on embedded hardware systems design techniques.
Deadline 24/07/2022
PROPONI LA TUA CANDIDATURA