Embedded DFT - INFINEON Germany (stage)
Thesis in external company Thesis abroad
Reference persons PAOLO BERNARDI
Research Groups GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type RESEARCH / EXPERIMENTAL
Description Logic circuit testing testing is a fundamental objective of semiconductor industries, given the very large percentage of chips' surface occupied by them. The thesis aims to establish advanced implementation methodologies for validating testing flows, including the usage of on-chip test engines to be programmed by firmware, and practical lab measurements. All stages from the concept to the implementation on-chip are covered in the thesis. The student will gain a broad insight into industrial SoC development. In collaboration with INFINEON, Munich.
Required skills Being familiar with digital circuit design
Knowledge about design for test (DFT)
EDA tools (Simulation-Fault simulation) and Python
Notes The thesis worksite is Munich, Germany. The Infineon company grants a salary to the enrolled student.
Deadline 23/11/2022 PROPONI LA TUA CANDIDATURA