SystemC-based model checking for functional verification of safety-critical applications
Thesis in external company
Reference persons LUCIANO LAVAGNO
External reference persons The thesis will be done at Punch, Torino.
Research Groups Microelectronics
Thesis type THEORY AND PROJECT
Description Modeling of embedded systems design includes various abstraction levels and corresponding methods for synthesis and verification. The manual translation of specifications into a formal implementation is a time-consuming and error-prone process.
To automate the generation of a test environment for SystemC components, a structured methodology must be implemented: it involves the definition and adoption of a test specification format that can be parsed by an algorithm able to generate the actual SystemC code.
Starting from a implementation of a Finite State Machine (FSM) written in SystemC, and given a final state to be reached, the goal of the thesis is to define and prototype a methodology and an automatic tool to verify if the FSM can reach the state, e.g. a "fault" one, or one where a given output is generated, by generating a SystemC-based stimulus that can lead to the desired state.
Required skills SystemC modeling
Unified Verification Methodology
Notes Some knowledge of Model Checking is a plus.
Deadline 09/05/2023 PROPONI LA TUA CANDIDATURA