Design of a SAR Digitizing Error Amplifier for digitally controlled Power Converters
Tesi esterna in azienda
Riferimenti PAOLO STEFANO CROVETTI
Riferimenti esterni Vanni Poletto (STMicroelectronics)
Gruppi di ricerca Advanced AMS and Power ICs (Polito) - STMicroelectronics (Castelletto)
Tipo tesi SPERIMENTALE - PROGETTAZIONE
Descrizione Digital control is now becoming more and more popular in power converters for automotive applications due to its versatility, low cost and high performance. In spite of that, a digital implementation of the control algorithm requires A/D conversion of the output and/or reference. For this purpose, the adoption of conventional A/D converters (e.g. SAR, sigma-delta ADCs) employed in analog sensor readout is generally not straightforward and inefficient, in consideration of the range of the signals to be acquired (tens of Volt) and of the resolution/speed requirements. Considering that the quantity of interest in closed-loop digital control applications is the error signal (converter output - reference), rather than the output in itself, ad hoc A/D converters specifically conceived to digitize the error signal may be substantially simpler, more accurate and energy efficient. In this scenario, the thesis aims at the design, simulation, layout and post-layout verification of a Successive Approximation Register (SAR) A/D Converter and its embedded pre-conditioning that is specifically conceived to be employed in a digitally controlled power converter.
Vedi anche st internship - csa.pdf
Conoscenze richieste • Basic analog structure knowledge (band-gap reference, current mirrors, operational amplifiers, compensation methods)
• Strong knowledge of transistor level analog electronic concepts (noise, matching, offset, bandwidth)
• Cadence design suite or equivalent spice simulation experience is a plus
Note Tesi presso STMicroelectronics - Cornaredo (MI). E' previsto rimborso spese/compenso.
Scadenza validita proposta 01/02/2024 PROPONI LA TUA CANDIDATURA