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TensorFlow Lite on STM32 with FPGA acceleration

Reference persons MARIO ROBERTO CASU, MASSIMO RUO ROCH

Research Groups VLSILAB (VLSI theory, design and applications)

Description The TensorFlow Lite (TFLite) framework for Deep Neural Networks (DNNs) at the edge and for IoT supports a certain number of microcontrollers, including the well-known STMicroelectronics STM32. For complex deep neural network workloads, a microcontroller needs to be helped by dedicated hardware accelerators. In this thesis, the student will use a board developed at Politecnico di Torino containing an STM32 microcontroller and a low-power FPGA to accelerate with the FPGA some TFLite kernel functions (like, Convolution, Dense, Depthwise) for which the software latency would be otherwise too large.

See also  board.png 

Deadline 06/02/2025      PROPONI LA TUA CANDIDATURA