| KEYWORD |
Testing delay faults on asynchronous reset signals
Thesis in external company
Reference persons RICCARDO CANTORO, MATTEO SONZA REORDA
External reference persons Michelangelo Grosso
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description This thesis will be performed in the joint laboratory between PoliTo and STMciroelectronics existing withing PoliTo.
The activities will focus on a specific but very relevant topic raising practical issues in the test of current circuits manufactured by STMicroelectronics, i.e., the test of delay faults affecting the reset circuitry. These faults are not easily managed by current EDA tools.
The thesis activity will be organized in the following phases
1 - problem understanding, resorting to some test cases
2 - analysis of the solutions provided by current EDA tools (in particular, by Synopsys and Mentor)
3 - development of solutions to properly manage these faults
4 - solution assessment on real circuits by STMicroelectronics.
STMicroelectronics offers a grant for the student involved in the thesis.
In the recent past, most of the students involved in a master thesis with STMicroelectronics have been offered for a position in the company.
Required skills Basic knowledge in digital design and testing
Deadline 05/03/2024
PROPONI LA TUA CANDIDATURA