| KEYWORD |
Simulation of power flows in a RISC-V based system
keywords POWER SIMULATION, RISC-V
Reference persons DANIELE JAHIER PAGLIARI, MASSIMO PONCINO, SARA VINCO
Research Groups DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Thesis type RESEARCH
Description The thesis consists in the extension of a SystemC-based power consumption simulator with a RISC-V CPU. The simulated system is equipped with a CPU/MCU, a set of sensors and actuators, and is powered by a battery or energy harvester, with all components interfaced through DC/DC converters. The current version of the simulator focuses on the power aspects, and expects a simple trace of activity as input for each component. In contrast, the new version will have the CPU as the main "center of control", mimicking more closely what happens in the real world. To this end, a proper functional bus will have to be simulated, through which the CPU can send commands to other system components (e.g., to request a value to a sensor or control an actuator), which in turn will affect the power state of the peripherals. Initially, the CPU will be simulated directly in SystemC, through an infinite loop which performs a sequence of "actions" on the aforementioned functional bus, and wait/sleep operations, which affect its own the power state. After achieving this first milestone, the simple CPU model can be then replaced by an existing full-fledged RISC-V Instruction Set Simulator (ISS). The ISS has already been identified and only its integration is part of the thesis work. Furthermore, other possible extensions involve simulating not only the power consumption, but also the thermal behavior and the reliability aging of system components. This thesis work falls within the scope of a large EU-funded project on Open Hardware and RISC-V, involving all major European semiconductor players (Infineon, NXP, ST Microelectronics, and others).
See also energy simulator thesis proposal.pdf
Required skills Programming skills
Deadline 16/03/2024
PROPONI LA TUA CANDIDATURA