PORTALE DELLA DIDATTICA

Ricerca CERCA
  KEYWORD

Improve robustness of FPGA dataflow accelerators for Convolutional Neural Networks

Parole chiave CNNS, FPGA, HLS, HW, ROBUSTNESS, TRAINING

Riferimenti CLAUDIO PASSERONE

Riferimenti esterni Pierpaolo Morì

Tipo tesi RICERCA

Descrizione The aim of this thesis is to demonstrate the effectiveness of Fault Aware Training (FAT) on dataflow FPGA accelerators for CNNs. The work will be organized in two main milestones:
• Training a CNN model modeling HW soft-errors at training time. 
• Evaluate the effectiveness of the trained model on a faulty FPGA accelerator.

Vedi anche  thesisproposal_fat.pdf 

Conoscenze richieste Python, FPGA design


Scadenza validita proposta 26/11/2023      PROPONI LA TUA CANDIDATURA