| KEYWORD |
Reliability evaluation of memory transfers in RISC-V microcontrollers
keywords ARTIFICIAL INTELLIGENCE, CONVOLUTIONAL NEURAL NETWORKS, DEEP NEURAL NETWORKS, FAULT INJECTION, FAULT TOLERANCE, TESTING
Reference persons DANIELE JAHIER PAGLIARI, ANNACHIARA RUOSPO, EDGAR ERNESTO SANCHEZ SANCHEZ
External reference persons ALESSIO BURRELLO
Research Groups DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD, DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Thesis type EXPERIMENTAL, SOFTWARE DEVELOPMENT
Description The continuous evolution of neural networks has led to a significant increase in the use of microcontrollers to implement artificial intelligence algorithms directly onboard embedded devices. However, the reliability of such systems is a key concern, as errors or failures during execution can have serious consequences in safety-critical domains, such as industrial automation, autonomous driving, and medical device safety. Therefore, it is crucial to understand the impact of potential faults in the hardware architecture on neural networks implemented on microcontrollers, and to develop adequate simulation tools to evaluate the reliability of such systems.
Objective:
This thesis work aims studying the impact of faults affecting memory transfers in microcontrollers. In particular, the goal is to evaluate how these faults affect the performance and reliability of neural networks in terms of accuracy, execution times and perturbation robustness. Furthermore, we plan to develop a simulation model to reproduce these faults and evaluate the behaviour of the system under controlled conditions.
Methodology:
- Study of the microcontroller architecture and the implementation of neural networks on it
- Analysis and identification of a new fault injection method on the microcontroller?s DMA
- Design and implementation of an experimental system to evaluate the impact of such faults on neural networks
- Collection of experimental data through the simulation of realistic scenarios with different configurations of faults and network parameters
- Analyse neural network performance by evaluating accuracy, execution time, and robustness to perturbation metrics
- Creation of a simulation model that reproduces the errors on the DMA and allows evaluating the impact on the neural networks in a controlled way
- Validation of the simulation model by comparing the results obtained from the simulation with the experimental ones
- Discussion and interpretation of the results obtained, highlighting the practical implications and possible error mitigation strategies.
Required skills Required skills include C and Python programming. Further, a basic knowledge of computer architectures and embedded systems is necessary. Knowledge of deep learning and the corresponding models is also required. It is also useful (but not strictly necessary) to have a minimum familiarity with testing and fault tolerance concepts.
Deadline 31/12/2023
PROPONI LA TUA CANDIDATURA