| KEYWORD |
Pioneering ARM DSU big.LITTLE Cluster Optimization
Thesis in external company 
Thesis abroad
keywords ARM, C, COMPILERS, DESIGN SPACE EXPLORATION, EMBEDDED SYSTEMS, ENERGY EFFICIENCY, FIRMWARE, HARDWARE AND SOFTWARE, HARDWARE DESIGN, LOW POWER, MICROCONTROLLERS
Reference persons DANIELE JAHIER PAGLIARI
External reference persons Yukai Chen (IMEC)
Research Groups DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA, ELECTRONIC DESIGN AUTOMATION - EDA, GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Thesis type EXPERIMENTAL, HARDWARE DESIGN, SOFTWARE DEVELOPMENT
Description This thesis will be carried out at the IMEC research center in Leuven, Belgium.
The focus of this thesis is the design and implementation of an Arm DSU big.LITTLE cluster, employing Arm HP as the big and Arm HD as the LITTLE. Responsibilities include defining realistic workloads and benchmarks for the cluster, developing and optimizing compiler configurations for efficient workload mapping onto the big and LITTLE cores. IMEC's current toolchain supports single Processing Element (PE), big or LITTLE, simulation, and the objective is to handle more complex workloads on both big and LITTLE cores.
The candidate will also engage in dynamic tasks like workload partitioning, with possible consideration of aspects like TinyML inference thermal-aware mapping. Further responsibilities include addressing the challenges associated with CPU migration and multi-core task scheduling. Leveraging the DSU's support for energy-aware scheduling software on both big and LITTLE cores, the candidate will analyze simulation results, identify bottlenecks, and propose optimizations to boost system performance, power, and thermal efficiency.
Adopting an innovative, system-level perspective is crucial to engineering high-density, cost-effective ICs optimized for PPACT. This thesis offers a unique opportunity to be at the cutting edge of technological advancement, addressing scaling and power challenges.
Required skills IMEC seeks candidates with a background in Electronics/Computer Engineering, possessing a robust understanding of Computer Architecture and Embedded Systems. Proficiency in C, Python, Cross-compilation, SystemVerilog/VHDL, RTL simulation, and Post-synthesis analysis is necessary. Experience with ARM IP development will be considered a plus.
Notes Thesis carried out at the IMEC research center in Leuven, Belgium, under the supervision of Dr. Francky Catthoor, Dr. Yukai Chen, and Dr. Dwaipayan Biswas. The candidate will be financially supported by IMEC for the travel (around 800/1000 Euro per month, not considering potential scholarships).
Deadline 07/08/2022
PROPONI LA TUA CANDIDATURA