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Control and Data Flow Graph Analysys to Quickly Grade Functional Test Programs
keywords PARALLEL COMPUTING, ARCHITECTURE SOFTWARE DISTRIBU, PARALLELIZZAZIONE, SOFTWARE DESIGN, SOFTWARE TESTING
Reference persons PAOLO BERNARDI, STEFANO QUER
Research Groups DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD, DAUIN - GR-13 - METODI FORMALI - FM
Thesis type RESEARCH / EXPERIMENTAL, RESEARCH ORIENTED
Description In recent years, there has been an exponential growth in the size and complexity of System-on-Chip designs targeting essential applications. The cost of an undetected bug in these systems is much higher than in traditional processor systems as it may imply the loss of property or life. The problem is further exacerbated by the ever-shrinking time-to-market and ever-increasing demand to churn out billions of devices.
Simulation and formal verification are two complementary verification techniques. Given a design property, formal verification proves the property holds for every point of the search space. The main drawback of formal verification is its unscalability. Simulation verifies the property by testing a small subset of the search space. The obvious flaw of simulation is its inability to prove that a property holds for every point of the search space.
Consequently, despite decades of research in simulation and formal methods for debugging and verification, these phases account for a high percentage of the overall development cost, and today's systems experience spectacular and all-too-frequent problems.
Recently, the work
F. Angione, P. Bernardi, A. Calabrese, A. Nicoletti, D. Piumatti, S. Quer, D. Appello, V. Tancorre, R. Ugioli, “An innovative Strategy to Quickly Grade Functional Test Programs”, IEEE International Test Conference (ITC), 2022, pp. 355-364, DOI: 10.1109/ITC50671.2022.00044.
proposed a novel technique providing a preliminary and quick evaluation of functional test procedures of various natures. The approach is based on analyzing the execution trace generated by the functional program. Essentially, starting from the instruction sequence generated by the chip, we first build a control data flow graph. Then, we analyze it to recognize instructions (critical edges) that negatively impact the final coverage in the control and data flow. This analysis guides test engineers in developing data-connected programs, i.e., code segments whose data are propagated through registers along the entire program and finally accumulated into a signature.
The thesis will focus on extending the current approach to multi-core architectures. Modern devices usually have more than one computing core and generate several traces with synchronization points. This implies, for example, that a variable written in the code generated by one core can indeed be read by another core. Thus, critical (unfruitful) instructions on single code sequences will be perfectly fine on the global multi-core activity. Thus, the work has to extend the current graph-based analysis of a single code trace to multiple and related code traces.
Required skills • Advanced programming skills in C and C++, including graph manipulation and parallelization (the reference courses are “Algorithms and Data Structures”, “Operating Systems”, and “System and Device Programming”).
• Basics on hardware and software architectures and reliability issues (the reference course is “Architetture dei sistemi di elaborazione”).
Notes Expected Learning Outcomes:
• Development and debugging of software generated by micro-controllers or systems on a chip.
• Skills in code parallelization and synchronization.
• Skills in performance analysis and code optimization.
• Skills in industrial devices and software distributed by STMicroelectronics.
Deadline 20/11/2023
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