Design, reliability evaluation and hardening of vision-oriented hardware accelerators
Reference persons MATTEO SONZA REORDA
External reference persons Juan David Guerrero Balaguera
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description Nowadays, hardware accelerators are fundamental processing units that provide the computational capabilities demanded by modern applications like autonomous driving systems and robotics. In fact, modern system-on-chip devices (SoCs) often incorporate specialized hardware accelerators for different purposes. For example, the NVIDIA Jetson Orin Nano incorporates a Programmable Vision Accelerator (PVA) unit to perform image and video processing, including stereo correspondence matching. In addition, this device includes two Nvidia Deep Learning (NVDLA) accelerators to speed up Neural Networks computations.
The widespread use of hardware acceleration architectures demands more robust and fault-tolerant designs that fulfill the requirements of modern vision-based applications. The current research activities of the group in this domain cover four main areas: i) design hardware units for vision-based or machine-learning accelerators, ii) devise methodologies to evaluate the criticality of the failures inside a hardware accelerator, iii) propose test techniques for fault detection during in-field operation, and iv) develop hardening strategies (hardware or software) to counteract any possible failure that endangers the system's correct operation.
This proposal aims at identifying students interested in working in this wide area, allocating each of them on the specific topic that best fits his/her interests and skills.
Required skills Digital design skills
Deadline 21/09/2024 PROPONI LA TUA CANDIDATURA