| KEYWORD |
Area Engineering
FPGA virtualization solutions
Thesis in external company 
Thesis abroad
keywords FPGA-BASED DESIGN, PARTIAL RECONFIGURATION
Reference persons LUCIANO LAVAGNO
External reference persons Daniel Raho, Virtual Open Systems, Grenoble, France
Research Groups microelettronica
Thesis type DEVELOPMENT
Description The intern will be integrated into the design and development team to develop innovative framework and tools for embedded virtualization systems. In this context, the intern will support the development activities of FPGA virtualization solutions leveraging SR-IOV and partial reconfiguration to maximize system efficiency and performance in Telecom/Space communications, HPC and Cloud Computing.
This requires a good knowledge of FPGA design and embedded firmware design.
Required skills FPGA design and embedded firmware design.
Excellent communication skills and good teamwork, written and spoken English.
Notes In case you are interested, please send me your CV by email.
The position can become a full time job at the end of the thesis.
Deadline 03/10/2025
PROPONI LA TUA CANDIDATURA