| KEYWORD |
Hardware acceleration of machine learning algorithms for sensing and processing at the edge with a dedicated microchip (developed by Sensichips)
Thesis in external company
Reference persons MARIO ROBERTO CASU, LUCIANO LAVAGNO
External reference persons Ing. Roberto Simmarano (Sensichips)
Research Groups VLSILAB (VLSI theory, design and applications)
Thesis type EXPERIMENTAL - DESIGN
Description It is foreseen that machine learning will be an integral part of most sensors. Sensichips has developed a proprietary microchip, codenamed SENSIPLUS, including sensors, signal conditioning, advanced multi-measurand analytical tools and a proprietary micro Neural Processor Unit (NPU) into a single 1.5x1.5mm microchip. In its first generation the NPU can execute neural networks and single sample machine learning algorithms. With the proposed Thesis we would like to extend the current NPU capabilities to support convolutional and deep learning algorithms. The key challenge to be addressed is to modify and accelerate such algorithms to achieve the smallest possible hardware addition, custom instruction set and support the most efficient execution.
See also sensichips_company_brief.pdf
Required skills VHDL or Verilog
Deadline 07/12/2024
PROPONI LA TUA CANDIDATURA