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RISC-V based HW/SW Design & Test for NFC Digital Signal Processing
Thesis in external company
Reference persons GUIDO MASERA
External reference persons • Tiberio Fanti, Engineering Director Digital Design, NXP Semiconductors Austria, Gratkorn
• Luca Lingardo, Senior Digital Designer, NXP Semiconductors Austria, Gratkorn
Research Groups VLSILAB (VLSI theory, design and applications)
Description Near Field Communication (NFC) is an ubiquitous technology with many applications ranging from
identification to ticketing, from mobile payment to logistical solutions and wireless charging. A considerable
amount of analog and digital signal processing is required on all NFC integrated circuits to achieve high
performance and reliable communication, while keeping engineering and manufacturing cost low.
Every modem unit of NXP’s NFC controllers product family must be able to support multiple communication
standards in different operative configurations and environmental conditions. This is achieved today by
means of an extensive use of custom digital signal processing (DSP) logic, which is tuned and constrained to
meet the final product requirements, at the expense of full functional flexibility. In such a context, the
estimated engineering effort, burdened by a very high pre-silicon verification effort, can be unacceptable
from the business perspective and limit the end product evolution.
One way to balance on-chip resources with the growing need for flexibility is to consider the adoption of RTL
microprocessors (softcores) with DSP ability. As opposed to more specialized signal processing made with
custom digital logic, a DSP softcore provides the wanted flexibility at the cost of potentially higher resource
usage: above all, program and data memory.
The aim of the two proposed Master Thesis is to:
• Build and verify a Microcontroller Unit (MCU) starting from an existing RISC-V microprocessor which
has been enhanced to execute custom instructions for NFC specific DSP algorithms;
• Build and verify a FW stack that operates on the RISC-V MCU HW, integrates an existing NFC decoding
algorithm, and interoperates with the host SoC main CPU SW.
See also nxp semiconductors austria - master thesis proposal - nfc dsp subsystem design and test.pdf
Required skills Requirements are: an excellent curriculum, advanced digital design knowledge (ASIC in particular) and a limited number of exams still to be taken.
Notes The location of the thesis work is NXP Semiconductors Austria, Gratkorn .
The enrolled student will be included in the project team and followed very carefully.
Deadline 17/01/2025
PROPONI LA TUA CANDIDATURA