| KEYWORD |
Area Architecture
Exploring the effectiveness of number formats in GPU-accelerated programs
keywords GRAPHICS PROCESSING UNITS, NUMBER FORMATS, PROCESSOR ARCHITECTURE, RELIABILITY
Reference persons JOSIE ESTEBAN RODRIGUEZ CONDIA
External reference persons Juan David Guerrero Balaguera
Research Groups DAUIN - GR-05 - ELECTRONIC CAD and RELIABILITY GROUP - CAD
Thesis type EXPERIMENTAL, HARDWARE AND SOFTWARE DESIGN
Description Currently, massive hardware accelerators (such as, Graphics Processing Units) are boosting developments and improvements in several domains, from machine learning to scientific applications. One of the crucial features in modern GPUs is their support in hardware for one or more number formats to effectively represent and operate values. This support provides accuracy and extends the application performance. However, open research questions arises when considering the operation of emerging number formats.
This thesis aims to explore and evaluate the effectiveness of number formats in GPU-accelerated programs. The main objetive of the thesis is the evaluation of parallel programs for GPUs under different number formats.
Objectives:
- Implement in hardware or use functional units in emerging number formats.
- Adapt and integrate functional units inside a state-of-the-art GPU core.
- Develop simple validation and verification codes for the integration of functional units.
- Evaluate/or develop parallel programs for GPUs on the different number formats.
What could you learn?
- Expertize and skills on parallel architectures
- Skills on digital design for parallel architectures
- Skills on programming GPUs
Required skills Basic knowledge in computer's/Processor's architecture
Basic Knowledge in number formats (i.e., integer, fixed-point, Floating-Point)
Knowledge in hardware description languages (e.g., VHDL, verilog)
Knowledge in scripting languages (Python or bash)
Deadline 26/02/2025
PROPONI LA TUA CANDIDATURA