| KEYWORD |
Area Ingegneria
Improving clock frequency in synchronous designs with Mix & Latch
Riferimenti MARIO ROBERTO CASU, LUCIANO LAVAGNO
Riferimenti esterni Lorenzo Lagostina
Gruppi di ricerca VLSILAB (VLSI theory, design and applications)
Descrizione Clock frequency is notoriously one of the most important metrics in VLSI design, and it can be optimized during synthesis and Place&Route with several techniques, like retiming, clock skewing and others. Mix&Latch is a novel technique that aims at improving clock frequency through latch time borrowing, while ensuring that no hold violation is caused into the digital design.
In this thesis, you will work with industrial tools for IC design, expanding the current functionalities of Mix&Latch. Based on your interest, skills, and background, you will be able to work on a software level (e.g. by developing models for automating the Mix&Latch flow to improve quality of results and/or time-to-result) or concentrate on microelectronic aspects (e.g. analysis of the effects of corner process variations, clock gating, design for testability). You will gather the experimental results by applying to different benchmarking circuits the Mix&Latch flow, using industrial tools for both the logic synthesis and layout phases.
Attached are the links to the publications, which can provide insights to the methodology:
https://doi.org/10.1109/ACCESS.2023.3265809
https://doi.org/10.1109/TCAD.2024.3360314
Conoscenze richieste Programming skills, understanding of VLSI theory (RTL. Synthesis, DFT, Place&Route)
Scadenza validita proposta 04/03/2025
PROPONI LA TUA CANDIDATURA