| KEYWORD |
Integration of new RISC-V processors in ESP platform for Machine Learning Applications
Reference persons MARIO ROBERTO CASU
Research Groups VLSILAB (VLSI theory, design and applications)
Description The ESP platform for Systems-on-Chip (https://www.esp.cs.columbia.edu/) currently supports only two RISC-V processors (Ibex and Ariane). The first goal of the thesis is to create an automated flow such that other RISC-V processors can be easily integrated in the platform, simulated, and finally tested on FPGA for proper verification. The second goal of the thesis is to train, compile, and execute Machine Learning applications on the ESP platform so as to identify the best RISC-V processor in terms of execution latency for those applications.
Deadline 26/07/2025
PROPONI LA TUA CANDIDATURA