| KEYWORD |
Integration of a Vector Unit as a RISC-V coprocessor in the ESP platform for Machine Learning Applications
Reference persons MARIO ROBERTO CASU
Research Groups VLSILAB (VLSI theory, design and applications)
Description The ESP platform for Systems-on-Chip (https://www.esp.cs.columbia.edu/) currently supports two RISC-V processors (Ibex and Ariane). The first goal of the thesis is to adapt the ARA vector unit of Ariane (https://github.com/pulp-platform/ara) to be integrated in the ESP platform, simulated, and finally tested on FPGA for proper verification. The second goal of the thesis is to verify the complexity of adapting such vector unit to the much smaller Ibex processor. Finally we want to accelerate Machine Learning applications to be executed on the ESP platform using ARA as accelerator.
Deadline 26/07/2025
PROPONI LA TUA CANDIDATURA