| KEYWORD |
Area Ingegneria
Design of reliable hardware accelerators for AI and vision applications
Parole chiave AI ACCELERATOR, RELIABILITY, VISIONE, VLSI
Riferimenti MATTEO SONZA REORDA
Riferimenti esterni Juan David Guerrero Balaguera
Gruppi di ricerca DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Descrizione Nowadays, AI is crucial to vision-based systems in many cutting-edge applications, especially in the field of autonomous systems such as robotics, automotive, and health care. These vision systems offer any artificial platform the ability to "see" the surrounding environment and make decisions to navigate in unknown environments, performing specific tasks autonomously, all of which only rely on cameras or environmental sensors. Autonomous driving systems are a clear example of the success of vision technology since they give automobiles the capability to navigate through complex routes, reduce the stress of the driver, and help improve traffic conditions.
Although the design efficiency of hardware accelerators is essential in terms of power consumption and performance, reliability is also a crucial aspect to be considered, especially in safety-critical applications. Therefore, it is necessary to devise strategies to guarantee and possibly enhance the reliability of hardware accelerators.
This proposal aims for three main goals: i) devise methodologies to evaluate the criticality of the HW faults in any type of accelerator, ii) propose test techniques for fault detection during in-field operation, and iii) develop hardening strategies to counteract any possible failure that endangers the system's correct operation.
The following are the suggested activities that will guide the achievement of the proposed objectives successfully:
- Develop fault effect evaluation strategies using software-based or emulation-based strategies
- Identify the most critical structures in terms of fault sensitivity for the application
- Define metrics to assess the impact of faults on the studied accelerator
- Design fault tolerance solutions based on hardware or software mechanisms (e.g., redundancy, approximate techniques, design diversity, etc.).
The widespread use of hardware acceleration architectures demands more robust and fault-tolerant designs that fulfill the requirements of modern vision-based applications. The current research activities of the group in this domain cover four main areas: i) design hardware units for vision-based or machine-learning accelerators, ii) devise methodologies to evaluate the criticality of the failures inside a hardware accelerator, iii) propose test techniques for fault detection during in-field operation, and iv) develop hardening strategies (hardware or software) to counteract any possible failure that endangers the system's correct operation.
This proposal aims at identifying students interested in working in this wide area, allocating each of them on the specific topic that best fits his/her interests and skills.
Conoscenze richieste Digital design skills
Scadenza validita proposta 24/09/2025
PROPONI LA TUA CANDIDATURA