| KEYWORD |
Power Management Integrated Circuits for next generation Vital Signs monitoring
Thesis in external company
Reference persons GUIDO MASERA
External reference persons Ing. Angelo Mazzone, Analog Devices
Research Groups VLSILAB (VLSI theory, design and applications)
Description Thesis Description
ADI’s Digital Healthcare BU Vital Signal Monitor Group is seeking an Intern to be trained as Digital Design Engineer.
The candidate will Interact with a cross functional team developing Low Iq solutions for Power Management Integrated Circuits (PMICs) to be used in next generation Vital Signs monitoring ASIC.
The position is based on the Milan Design Centre.
The candidate will be internally trained on:
• RTL (Verilog /System Verilog)
• Design Verification (UVM)
• Low Power Design (exp. DC/DC Converter control blocks)
• Logical Synthesis, Static Timing Analysis, Power Analysis
• Physical Implementation
• Design For Testability
• Asynchronous Digital Design
• Lab Measurements
Minimum Requirements:
• BSEE Degree in Electronics / Ready for MS Electronics Degree.
• RTL basic knowledge
• Knowledge of RISC-V microcontroller architecture.
• Experience on FPGA
• C/C++ programming skills
• Analytical and problem-solving skills.
• Strong inter-personal, teamwork and communication skills.
• Technical English level fluency.
Preferred Qualifications
• Experience on RISC-V Firmware Development and Validation
• IC bench evaluation by using Oscilloscopes, Multimeter, Power Source, Function Generator.
Deadline 20/11/2025
PROPONI LA TUA CANDIDATURA