| KEYWORD |
Dependable Multi-Layer NoC architecture design
keywords DEPENDABLE SYSTEM DESIGN, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, NETWORK-ON-CHIP, ONLINE RECONFIGURATION
Reference persons STEFANO DI CARLO, PAOLO ERNESTO PRINETTO
External reference persons INDACO Marco (PhD Candidate)
GAMBARDELLA Giulio (PhD Student)
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL
Description Motivation:
The overall objective of this project is the development of reliable architectures and associated design practices for Networks-on-Chips. Thereby, it meets the challenges of increased susceptibility of on-chip communication infrastructures against the massive influences caused by escalating the integration density.
Goals:
The thesis aims at the development of a new reliable architecture for Network-on-Chip.
The goal is to set-up a new NoC online reconfiguration schema that aims at reliable communication architecture, guaranteeing predefined levels of dependability, latency, self-adaptability, and performances.
Learning Outcomes:
During this thesis the candidate will learn Design for Reliability methodologies and gain skill on the Network-on-Chips and their innovative architectures.
Required skills Programming Languages: C, VHDL
Digital System design methodologies
Notes The thesis will be developed within the framework of a joint research project between the Testgroup of Politecnico di Torino and the Inst. für Technische Informatik, Universität Stuttgart (Germany), prof. Hans-joachim Wunderlich
Deadline 31/12/2012
PROPONI LA TUA CANDIDATURA