A framework for Automatic generation of BCH-based ECC IP Cores
External reference persons INDACO Marco (PhD Candidate)
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL
Nowadays Error Correction Codes (ECCs) are a widely adopted fault-tolerance mechanism in several contexts (e.g., communication protocols, memory devices, etc.) to improve yield, reliability and endurance. To reach better performances, an hardware implementation is usually preferred.
In particular, Bose-Chaudhuri-Hocquenghem (BCH) codes are a family of ECCs largely applied to modern Flash memories to significantly improve their endurance and reliability.
From system design point of view, three are the parameters characterizing a cost-efficient BCH code implementation:
• correction capability - it specifies the number of errors BCH code can fix;
• size of the message - that is to be encoded/decoded;
• parallelism of the BCH's encoder/decoder - it specifies the number of bits that can be inputted at each clock cycle.
The goal of the thesis is to implement a sophisticated and advanced ESL tool for the automatic generation of BCH-based ECC IP Cores. The framework should take as input the aforementioned parameters and should deliver a BCH IP core.
The candidate will acquire a basic knowledge of BCH codes and system level design methodology, skills on the system RTL description and gain a good experience about high level programming languages and development of ESL tools.
Required skills Programming Languages: C/C++ or Java, VHDL
Digital System design methodologies
Notes The thesis will be developed within the framework of a joint research project between the Testgroup of Politecnico di Torino and MPSoC group of Università di Ferrara.
Number of required Students: 1
Deadline 31/12/2012 PROPONI LA TUA CANDIDATURA