| KEYWORD |
Devising new techniques for writing programs for effectively testing Branch Prediction Units in pipelined processors
keywords SUPERSCALAR PROCESSORS, TEST
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ, MATTEO SONZA REORDA
Research Groups ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type EXPERIMENTAL
Description Superscalar processors allow to attain high performance for both general-purpose and embedded applications. Their test can be achieved by letting them execute specially devised programs able to excite the different components and observe the produced results, thus detecting possible faults. One of the most critical modules from this point of view is the Branch Prediction Unit.
The thesis aims at developing and experimentally validating some new techniques for writing these test programs; the planned activities are based on the usage of the SimpleScalar simulator developed by the University of Michigan. SimpleScalar allows simulating the behavior of a configurable superscalar processor when executing a given program.
Required skills Computer architecture
Basics in assembly language Programming
Deadline 30/06/2012
PROPONI LA TUA CANDIDATURA