| KEYWORD |
New techniques for testing of the cache coherence circuitri in multicore devices
keywords CACHE COHERENCE LOGIC, MULTICORE SYSTEMS, TEST
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ, MATTEO SONZA REORDA
Research Groups ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description Multicore systems require caches to reduce the negative impact of the accesses to a shared memory. To guarantee the coherence of data stored in the caches and in memory, special algorithms have been developed. When a growing number of cores are integrated into a single device, and the performance increases, the adopted algorithms and the related circuitry must be validated against design bugs and manufacturing defects. The thesis will address functional techniques for facing the problem, based on suitable programs to be run on the different cores, checking the resulting behavior. Experimental results will be gathered resorting to the OpenSPARC T1 (http://www.opensparc.net/opensparc-t1/index.html).
Required skills processor architecture
VHDL/verilog
Deadline 24/12/2013
PROPONI LA TUA CANDIDATURA