| KEYWORD |
Asynchronous scheduling in input queued switches and flow control.
keywords SCHEDULING ALGORITHMS, SWITCHING ARCHITECTURES
Reference persons ANDREA BIANCO, PAOLO GIACCONE
External reference persons Thomas Bonald at Telecom ParisTech (Paris).
Research Groups Telecommunication Networks Group
Description Input queue switches are one of the reference architectures when designing high-speed packet switches.
Commercially available packet switches as well classical theoretical results in this fields refer to synchronous solutions, in which the data transfers form inputs to outputs occur all at the same time and last for a fixed amount of time. Thus, synchronous architectures require input segmentation machines and output reassembly machines to chop and reassemble arriving IP packets, which are usually of variable size. In addition, the synchronous operation mode requires that all the different components of the switching architecture operates under the same clock reference. This last requirement becomes extremely challenging as the physical size of the switch and the speed at which the switch operates increase.
These issues can be easily overcome moving to an asynchronous mode of operations, i.e., allowing to transfer packet of variable size and taking scheduling decision at packet arrivals or departures.
The proposed thesis aims at investigating how the TCP/IP sources interacts with an asynchronous scheduler. In particular, the work consists in integrating TCP/IP traffic sources into an OMNet++ simulator of an asynchronous switch. A second step will consist in the assessment of switch performance both at the flow and the packet level.
Required skills Mandatory for this thesis are excellent C/C++ programming skills, good mark traffic theory I and simulation of network protocol.
Deadline 01/01/2013
PROPONI LA TUA CANDIDATURA