Advanced techniques for functional testing of superscalar processors
keywords TEST, PROCESSORS
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ, MATTEO SONZA REORDA
Research Groups ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description When processors are used in embedded systems for safety-critical applications it is crucial to consider the severe requirements existing for their test, both during the manufacturing phase and when they are deployed in the filed (on-line test).
For this reason, industries frequently use a functional approach, based on forcing the processor to execute a proper program, able to stimulate the different internal units and detect possible faults affecting them.
The thesis activity continues the project carried out by the CAD group in cooperation with STMicroelectronics (Milan), and faces the issue of extending the techniques already developed to test RISC processors to superscalar ones.
In particular, the IVM processor model developed by the University of Illinois will be considered as a test case; the new techniques will be adopted for developing test programs facing some units within that model, evaluating the achievable results.
Required skills VHDL, processor architecture
Deadline 09/11/2013 PROPONI LA TUA CANDIDATURA