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VLSI architectures for the High Efficiency Video Coding (HEVC) standard and 3D/MV extensions
keywords VLSI ARCHITECTURES, VIDEO COMPRESSION
Reference persons MAURIZIO MARTINA, GUIDO MASERA
Research Groups VLSILAB (VLSI theory, design and applications)
Thesis type IMPLEMENTATION
Description High Efficiency Video Coding (HEVC) is the new standard for video compression that will be released in 2013.
The goal of the standard is to double the compression ratio with respect to Advanced Video Coding (AVC-MPEG4 part 10) while keeping the same quality. One of the targets of HEVC is HD/full HD sequences that require a large amount of computational resources to achieve real time compression/decompression. Extensions of the standard to target 3D and multi-view video sequences are on-going.
In this field several activities aiming at designing novel and efficient architectures can be identified.
Required skills VHDL, C. In particular, integrated digital hardware design skills are required together with good experience with C programming. It is recommended having passed (or attended) the course "Integrated Systems Architecture".
Deadline 19/09/2016
PROPONI LA TUA CANDIDATURA