| KEYWORD |
Survey and implementation of an adaptable Product Codes generation framework
keywords DIGITAL SYSTEM DESIGN, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, ECC, SOFTWARE DEVELOPMENT, SYSTEM LEVEL DESIGN & TEST
Reference persons STEFANO DI CARLO, PAOLO ERNESTO PRINETTO
External reference persons GALFANO Salvatore (PhD Candidate), INDACO Marco (PhD Candidate)
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL
Description Motivation:
Nowadays Error Correction Codes (ECCs) are a widely adopted fault-tolerance mechanism in several contexts (e.g., communication protocols, memory devices, etc.) to improve yield, reliability and endurance.
With the advancing of technologies, electronic media become more faulty and thus currently used ECCs are no more applicable. In particular this applies also to Flash Memories, which will be the application field of the thesis. Unprecedented Error Correction Codes are going to be adopted, such as Low Density Parity Check and Product Codes.
In order to overcome varying context or needs (e.g., communication channel quality variation, memory wear-out, reliability requirement variation), adaptable architectures are the key to have the required flexibility and dynamically meet the local performances optima (i.e., best trade-offs).
Goals:
The thesis aims at first making a survey of Product Codes. Second step will be implementing an adaptable Product Codes generation framework.
Learning outcomes:
The candidate will acquire a basic knowledge of system level design methodology, skills on the system RTL description and operating systems.
Required skills Programming Languages: C, VHDL
Digital System design methodologies, Computer Architecture
Notes Number of required Students: 1 or 2
Deadline 01/03/2014
PROPONI LA TUA CANDIDATURA