| KEYWORD |
Study and development of CAD software for the dependability optimization of ultra-nanometer photolithographic processes
keywords PHOTOLYTOGRAPHI, VLSI
Reference persons LUCA STERPONE
Research Groups ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type APPLIED, EXPERIMENTAL
Description The goal of the thesis is the development of methods for the riduction of Single Event Latch-Up (SEL) on ASIC circuits
implemented using 15 nm technology process.
The activity will consist on the development of an analytical method for the dependability evaluation of SEL event
within single library cell. The NanGate Open Cell library, provided by the NanGate company, will be used for this scope.
The second phase of the activity will be devoted to the adaptation of an existing place and route algorithm for the
realization of the entire VLSI layout physical process able to reduce the SEL phenomena. The thesis will be executed in
collaboration with NanGate and Microsemi (leader companies on the realization of ultrananometer semiconductor components).
Besides, the thesis expects a radiation test execution at the Cyclotron the Louvain-la-NEuve (UCL, Belgium) with the
direct collaboration of Microsemi and ESA.
Required skills Knowledge about implementation of circuits on FPGA or ASIC: Mapping, Placement and Routing
Knowledge of VHDL (or Verilog), C and C++
Deadline 15/05/2015
PROPONI LA TUA CANDIDATURA