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FPGA-based implementation of Cryptographic Algorithms for the Advanced Open-source Security Platform SEcube™
keywords CRYPTOGRAPHIC ALGORITHMS, CRYPTOGRAPHY, DIGITAL SYSTEM DESIGN, EMBEDDED SYSTEMS, HARDWARE SECURITY, OPEN-SOURCE, SECURITY
Reference persons PAOLO ERNESTO PRINETTO
External reference persons Pascal TROTTA (PhD student), Giuseppe AIRO´ FARULLA (PhD Student), Giorgio DI NATALE (LIRMM, Montpellier, France).
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL
Description Motivations:
Nowadays, many services and applications need to be secured in order to guarantee the users’ privacy as well as the commercial and legal issues related to security threats and to safeguard the business stakeholders. While several standards, protocols and algorithms exist for handling the basic primitives for security (i.e., confidentiality, authentication, privacy), their implementation in real objects may require very high expertise and efforts.
The development of the Advanced Open-source Security Platform SEcube™ (Secure Environment Cube) tries to fill this gap providing heterogeneous security-oriented hardware, coupled with an open-source modular software architecture In the Platform, all the functional blocks are isolated and well documented in order to deliver to developers an easy-way to build, understand, modify, and rewrite the whole system if wanted.
The SEcube™ hardware consists of a single System-on-Chip (SoC) composed of three main blocks: (i) a low-power ARM Cortex-M4 processor, (ii) a flexible and fast Field-Programmable-Gate-Array (FPGA), and (iii) an EAL5+ certified embedded SmartCard.
All these features make the SEcube™ platform perfectly suitable for a wide range of applications where security is a major concern, including, among the others, Telecommunications, Internet of Things, and Home Automation.
In order to provide additional custom security features, several cryptographic algorithms, other than the ones already offered by the embedded certified SmartCard, can be implemented in the SEcube™ platform FPGA module. The flexibility offered by the FPGA can be effectively exploited to design very fast custom hardware accelerators implementing the chosen algorithms (e.g., DES, AES, …).
Goal of the thesis:
• Hardware implementation (VHDL/Verilog) of selected cryptographic algorithms targeting the SEcube™ platform FPGA module, under timing and power constraints.
• Implementation of software drivers to allow the SEcube™ processor to access the hardware modules implemented in the FPGA and send/receive their input/output data.
Learning outcomes:
The student will improve its VHDL/Verilog coding skills and digital systems design knowledge.
Moreover, she/he will understand the entire design flow of hardware modules, starting from requirements definition to logic simulation and synthesis with state-of-the-art EDA tools.
Finally, she/he will be able to test and debug designed modules on actual hardware (i.e., SEcube™ and/or other commercial FPGA development boards).
External/Industrial cooperations:
The thesis will be carried out in collaboration with:
• Blu5 View Pte. Ltd. (Singapore)
• CINI CyberSecurity National Lab, Nodo di Torino (Torino, Italy)
• Lero, the Irish Software Research Centre (Limerick, Ireland)
• LIRMM (Montpellier, France).
See also 8 - cryptographic algorithms.pdf
Required skills Programming Languages: VHDL or Verilog, C / C++
Digital System design methodologies, Computer Architecture, FPGA
Notes External/Industrial cooperations:
The thesis will be carried out in collaboration with:
• Blu5 View Pte. Ltd. (Singapore)
• CINI CyberSecurity National Lab, Nodo di Torino (Torino, Italy)
• Lero, the Irish Software Research Centre (Limerick, Ireland)
• LIRMM (Montpellier, France).
Deadline 17/08/2016
PROPONI LA TUA CANDIDATURA