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Fast and Secure Image Processing applications
Parole chiave DIGITAL SYSTEM DESIGN, EMBEDDED SYSTEMS, FPGA-BASED DESIGN, HARDWARE SECURITY, IMAGE PROCESSING, OPEN-SOURCE, SECURITY, SYSTEM LEVEL DESIGN & TEST
Riferimenti PAOLO ERNESTO PRINETTO
Riferimenti esterni Pascal TROTTA (PhD student), Giuseppe AIRO´ FARULLA (PhD Student)
Gruppi di ricerca TESTGROUP - TESTGROUP
Tipo tesi EXPERIMENTAL
Descrizione Motivations:
Nowadays, many services and applications need to be secured in order to guarantee the users’ privacy as well as the commercial and legal issues related to security threats and to safeguard the business stakeholders. While several standards, protocols and algorithms exist for handling the basic primitives for security (i.e., confidentiality, authentication, privacy), their implementation in real objects may require very high expertise and efforts.
The development of the Advanced Open-source Security Platform SEcube™ (Secure Environment Cube) tries to fill this gap providing heterogeneous security-oriented hardware, coupled with an open-source modular software architecture In the Platform, all the functional blocks are isolated and well documented in order to deliver to developers an easy-way to build, understand, modify, and rewrite the whole system if wanted.
The SEcube™ hardware consists of a single System-on-Chip (SoC) composed of three main blocks: (i) a low-power ARM Cortex-M4 processor, (ii) a flexible and fast Field-Programmable-Gate-Array (FPGA), and (iii) an EAL5+ certified embedded SmartCard.
All these features make the SEcube™ platform perfectly suitable for a wide range of applications where security is a major concern, including, among the others, Telecommunications, Internet of Things, and Home Automation.
Within the aforementioned applications fields, the SEcube™ platform can be effectively employed to implement custom fast image processing algorithms (exploiting the embedded FPGA module) while, at the same time, providing security features with the aim of protecting processed images and information, that eventually will be sent or received through a network.
Goal of the thesis:
• Definition of a reference use case in the field of secure image processing.
• Hardware implementation (VHDL or Verilog) of selected secure image processing algorithms on the FPGA module embedded in the SEcube™ platform.
• Implementation of software drivers to allow the SEcube™ platform processor to access the hardware modules implemented in the FPGA and send/receive their input/output data.
Learning outcomes:
The student will improve her/its VHDL/Verilog coding skills and digital systems design knowledge. Moreover, she/he will understand the entire design flow of FPGA-based hardware modules, starting from requirements definition to logic simulation and synthesis with state-of-the-art EDA tools.
Finally, she/he will be able to test and debug designed modules on actual hardware (i.e., SEcube™ or other commercial FPGA development boards).
External/Industrial cooperations:
The thesis will be carried out in collaboration with:
• Blu5 View Pte. Ltd. (Singapore)
• CINI CyberSecurity National Lab, Nodo di Torino (Torino, Italy)
• Lero, the Irish Software Research Centre (Limerick, Ireland)
• LIRMM (Montpellier, France)
Vedi anche 4 - image processing.pdf
Conoscenze richieste Programming Languages: VHDL / Verilog, C / C++
Digital System design methodologies, Computer Architecture, FPGA
Note External/Industrial cooperations:
The thesis will be carried out in collaboration with:
• Blu5 View Pte. Ltd. (Singapore)
• CINI CyberSecurity National Lab, Nodo di Torino (Torino, Italy)
• Lero, the Irish Software Research Centre (Limerick, Ireland)
• LIRMM (Montpellier, France).
Scadenza validita proposta 17/08/2016
PROPONI LA TUA CANDIDATURA