FPGA-based accelerators for future Mars exploration missions
Thesis in external company
Reference persons PAOLO ERNESTO PRINETTO
External reference persons Pascal TROTTA (PhD Student), Daniele ROLFO (ThalesAlenia Space Italy)
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL THESIS
Video-based navigation is increasingly used in space-applications (e.g., rover navigation). Future space-missions will include this approach during the EDL (Entry, Descending and Landing) phase, to increase the precision of EDL systems. High dependability and high computational capabilities are required. Advanced FPGA-based processors appear to be good candidate for accelerating these applications.
In particular, an efficient partitioning of the execution of these tasks among software routines (running on the On-Board Computer, e.g., LEON2/LEON3 based processors) and custom FPGA-based hardware accelerators allows to reach the required performances.
Goal of the thesis:
The thesis aims at developing FPGA-based hardware accelerators, implementing image processing algorithms, for enhancing the performances of the Video-based Navigation System in critical space missions.
The system has to extract different information from input images and find the best descending trajectory. All the computations have hard-real time constraints.
The developed accelerators will be finally tested on the Avionic Test Bench (ATB) (i.e., a rack containing different boards emulating different units composing the avionic segment of a spacecraft) of Thales Alenia Space Italy.
During this thesis the candidate will learn how to design high-performance FPGA-based accelerators, manage different kind of data, and guarantee the required level of dependability.
In addition, since the thesis will be done in ThalesAlenia Space s.p.a., the student will familiarize with the industrial world, easing his introduction in the work world.
The thesis activity will be carried out in ThalesAlenia Space S.p.a. located in Strada Antica di Collegno, 10146 Torino, Italy.
Required skills Programming Languages: VHDL, Matlab, C;
Digital System design methodologies, Computer Architecture, FPGA
Notes The thesis activity will be carried out in ThalesAlenia Space S.p.A. located in Strada Antica di Collegno, 10146 Torino, Italy.
Deadline 31/05/2016 PROPONI LA TUA CANDIDATURA