Speech Rate Recognition @Centro Ricerche e Innovazione Tecnologica RAI
keywords ASSISTIVE TECHNOLOGIES, AUDIO PROCESSING, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, FPGA, MATLAB
Reference persons PAOLO ERNESTO PRINETTO
External reference persons Andrea DEL PRINCIPE (Centro Ricerche RAI)
Giuseppe AIRO’ FARULLA (PhD candidate, Politecnico di Torino)
Research Groups TESTGROUP - TESTGROUP
Thesis type EXPERIMENTAL THESIS
The thesis aims at developing an innovative add-on for a compact device specifically tailored to allow the user to slow-down in real-time an audio stream retrieved from modern TVs or DVB-T receivers. This component should aim at detecting whether the audio stream contains, at any moment, noise, music or a speech, and in the last case its frequency (i.e., number of words spoken per minute). The final goal here is to adapt this frequency to a threshold, which could be also adaptive, to make the speech itself more comprehensible.
The device developed during the thesis work will be based on modern FPGA/CPU heterogeneous platforms (e.g., SEcube™ produced by Blu5View and/or Zynq produced by Xilinx). Audio processing algorithms must be modeled (e.g., using MATLAB and C), evaluated and, depending on the required performances, hardware accelerated exploiting available programmable logic resources (i.e., FPGA), while other less intensive software control routines can use the available embedded processor.
During this thesis, the candidate will learn how to approach to SW/HW partitioning of processing tasks, manage different kind of data and model audio processing algorithms, and will gain knowledge on Machine Learning. Finally, he/she will be able to design high-performance FPGA-based accelerators to guarantee the required performances.
The thesis activities will be carried out in collaboration with:
- Centro Ricerche e Innovazione Tecnologica RAI (Torino)
- CINI National Lab on Assistive Tecnologies (https://www.consorzio-cini.it/index.php/en/national-laboratories/laboratorio-astech)
Required skills Programming Languages: Matlab, C/C++, VHDL;
Embedded Systems, Digital System design methodologies, FPGA, Microcontrollers.
Notes Number of required Students: 1 or 2
Deadline 10/01/2018 PROPONI LA TUA CANDIDATURA