Differential Power Analysis on SEcube™
Riferimenti PAOLO ERNESTO PRINETTO
Riferimenti esterni Antonio VARRIALE (Blu5 Labs Ltd);
Giuseppe AIRO’ FARULLA (PostDoc, Politecnico di Torino)
Gruppi di ricerca GR-21 - TESTGROUP - TESTGROUP
Tipo tesi EXPERIMENTAL THESIS
SEcube™ is a combination of three main cores in a 3D single-chip design. Low-power ARM Cortex-M4 processor, a flexible and fast Field-Programmable-Gate-Array (FPGA), and an EAL5+ certified Security Controller (SmartCard) are embedded in an extremely compact package. This makes it a unique security environment where each function can be optimized, executed, and verified on its proper hardware device. Leveraging the SEcube™, it is possible to define groups of users, so that users belonging to the same group can communicate and share messages (while the communication will not be accessible from outside the group).
Aims of this Thesis is to conduct side-channels attacks and to perform a Differential Power Analysis (DPA) on the above-mentioned three main cores to assess their resistance to cybersecurity attacks.
During this thesis, the candidate will learn how to approach to middleware and SDKs for microcontrollers, how to deal with security policies and secure communication, and will gain an in-depth knowledge about microelectronics, and network-based communication.
The thesis activities will be carried out in collaboration with:
- Blu5 Labs Ltd (Malta)
- CINI Cybersecurity National Laboratory
Conoscenze richieste Programming Languages: C/C++, Java
Note Number of required Students: 1 or 2
Scadenza validita proposta 28/12/2018 PROPONI LA TUA CANDIDATURA