Acceleration of software applications via High-Level Synthesis for FPGAs
Research Groups microelettronica
Thesis type RESEARCH
Description Tools like Catapult and Vitis HLS allow designers to synthesize code written in C, C++, SystemC or OpenCl into an RTL Verilog or Vhdl module. The research by our group is aimed at making the synthesis process as smooth as possible, in order to enable its use almost like a software compiler. Currently this is not trivial, because the designer must still choose manually how to efficiently implement loops and arrays in the code:
- the loops can be pipelined or unrolled, in order to increase performance at the cost of more HW resources.
- the arrays can be partitioned into small memories, in order to enable multiple iterations of a loop to access them in parallel.
- entire C functions can be implemented as processes in a coarse-grained pipeline.
Possible thesis topics:
- development of a design exploration tool which analyzes the C source code and attempts several of the above transformations automatically, using the HLS tool to estimate performance and cost. The goal is to explore a small part of the Pareto space, finding as many Pareto points as possible.
- choosing an existing application, e.g., from signal processing or machine learning, and generating an optimized implementation on an FPGA.
- using profiling tools, such as Valgrind, to trace the memory accesses performed by an application, and using machine learning techniques to recommend the best loop restructuring and array partitioning options to the designer (or to the design space exploration tool).
Required skills Progettazione HW. Programmazione in C/C++.
Deadline 15/11/2023 PROPONI LA TUA CANDIDATURA