Thesis on 5G simulation acceleration via FPGA at Telecom Italia Labs
Thesis in external company
Reference persons LUCIANO LAVAGNO
External reference persons Roberto Quasso, Telecom Italia Wireless Access Innovation, Torino
Research Groups High-Level Synthesis and FPGA acceleration
Thesis type SYSTEM PROTOTYPING
Description As more and more network functions are shifting from dedicated hardware to software virtualized functions, leveraging the availability of low-cost ICT equipment and tools, it becomes clear that the lower is the level of those functions the larger is the processing power required. Software Defined Radio (SDR) applied to the lower layers of 5th generation mobile networks is an example of software virtualization reaching its limits in terms of feasibility and affordability.
Since processor speed is no longer increasing as it used to, a promising way to face this bottleneck (without resorting to an infeasible ASIC approach) is to offload the most demanding functions to an FPGA-based (Field programmable Gate Array) hardware accelerator closely coupled to the host CPU, similarly to what is done with GPU cards for high-end graphic or gaming applications.
OpenCL is a high-level programming language close to C/C++, that provides access to hardware accelerator devices and allows developers to control the synthesis process inferring parallel hardware functions from source code. Complete OpenCL software stacks are today available from Intel, to be used with their PCIe accelerator cards.
The objective of the thesis is to use hardware acceleration to speed up the computational bottleneck of a 5G radio channel simulator, including multi-path propagation effects, and to evaluate the speed gain on FPGA with respect to its current software-only implementation.
Deadline 09/07/2019 PROPONI LA TUA CANDIDATURA