FPGA-based acceleration of Open Air Interface physical layer modules
Riferimenti LUCIANO LAVAGNO
Riferimenti esterni Roberto Quasso, Telecom Italia Wireless Access Innovation, Torino
Gruppi di ricerca High-Level Synthesis and FPGA acceleration
Tipo tesi SYSTEM PROTOTYPING
Descrizione As more and more network functions are shifting from dedicated hardware to software virtualized functions, leveraging the availability of low-cost ICT equipment and tools, it becomes clear that the lower is the level of those functions the larger is the processing power required. Software Defined Radio (SDR) applied to the lower layers of 5th generation mobile networks is an example of software virtualization reaching its limits in terms of feasibility and affordability.
Since processor speed is no longer increasing as it used to, a promising way to face this bottleneck (without resorting to an infeasible ASIC approach) is to offload the most demanding functions to an FPGA-based (Field programmable Gate Array) hardware accelerator closely coupled to the host CPU, similarly to what is done with GPU cards for high-end graphic or gaming applications.
OpenCL is a high-level programming language close to C/C++, that provides access to hardware accelerator devices and allows developers to control the synthesis process inferring parallel hardware functions from source code. Complete OpenCL software stacks are today available from Intel, to be used with their PCIe accelerator cards.
The thesis goal is the application of hardware acceleration to parts of Open Air interface Radio Access Network (OAI-RAN) platform, which is a C open source implementation of LTE/NR (5G) Radio Access Network (both base station and User Equipment). Specifically, the candidate will have to identify the physical layer modules which are compute-intensive, port them in OpenCL language and evaluate the performance against different hardware acceleration platforms (GPU and FPGA).
Scadenza validita proposta 17/07/2021 PROPONI LA TUA CANDIDATURA