| KEYWORD |
Interconnect congestion analysis for artificial intelligence algorithms accelerated on FPGAs
keywords MACHINE LEARNING, ARTIFICIAL NEURAL NETWORKS, PLACEMENT AND ROUTING
Reference persons LUCIANO LAVAGNO
Research Groups microelettronica
Thesis type RESEARCH
Description Software developers and hardware designers use High Level Synthesis to generate RTL code from C++ or OpenCL source code for implementing algorithms on FPGA. However, for implementing computation intensive algorithms like Convolution Neural Networks, poor design choices can cause placement and routing issues like congestion. These issues can drastically reduce the performance of FPGA in terms of achieving timing constraints or design failures.
To help the HLS designer to identify the possible sources of congestion at the design level in the source code, we are developing a tool that can trace the wires in the congested regions of FPGA to the C++ code.
The thesis has the goal of both trying out the tool on some design examples, and improve its functionality.
See also https://iot.det.polito.it/acceleration-of-software-applications-via-high-level-synthesis-for-fpgas/
Required skills A basic knowledge of Linux and of the FPGA implementation flow (Vivado, Quartus) are required for this task.
Knowledge of some text processing tool and of high-level synthesis will be an advantage.
Notes By the end of the thesis you will be familiar with:
- Implementation strategies for machine learning algorithms on FPGAs via high-level synthesis
- High-Level Synthesis, placement and routing for FPGAs using Vivado tools
Deadline 18/09/2021
PROPONI LA TUA CANDIDATURA