| KEYWORD |
DMA-based multi-IP environment for the FPGA on SEcube™ board
keywords FPGA-BASED DESIGN, HARDWARE DESIGN, HARDWARE SECURITY, SECUBE, SECURITY
Reference persons PAOLO ERNESTO PRINETTO
External reference persons Gianluca ROASCIO (CINI Cybersecurity National Laboratory)
Nicolò MAUNERO (CINI Cybersecurity National Laboratory)
Antonio VARRIALE (Blu5 Labs Ltd)
Research Groups GR-21 - TESTGROUP - TESTGROUP
Thesis type MASTER THESIS
Description The purpose of the thesis is to propose a new CPU-FPGA communication system on SEcube™ board by Blu5®. The protocol should contemplate the presence of multiple IP cores inside the FPGA, and should leverage the usage of DMA controller to handle transactions for inputs and outputs from/to the CPU.
The candidate/s will be both encharged of designing and implementing the new internal architecture of the FPGA and to develop the necessary firmware extensions (in C) to control the multicore FPGA in DMA mode.
External/Industrial cooperations:
- Blu5® Labs Ltd (Malta)
- CINI Cybersecurity National Laboratory
Required skills VHDL
C, C++ programming
Notes The thesis activities will be carried out in collaboration with:
- Blu5 Labs Ltd (Malta)
- CINI Cybersecurity National Laboratory
For additional informations:
- Gianluca ROASCIO – gianluca.roascio@polito.it
- Nicolò MAUNERO – nicolo.maunero@polito.it
Deadline 29/01/2021
PROPONI LA TUA CANDIDATURA