| KEYWORD |
Area Engineering
UVM Verification Environment for RISC-V based SoCs
Reference persons EDGAR ERNESTO SANCHEZ SANCHEZ
External reference persons Giacomo Bernardi
Synopsys
Research Groups DAUIN - GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Description System-on-Chip (SoC) Verification is one of the most critical and time-consuming phase of the SoC supply chain. There is, indeed, the need for a reusable and strong verification environment. The Universal Verification Methodology (UVM) currently provides a best-practice verification methodology. It is fully supported by major tool vendors and producers companies. The main intent of this Master Thesis is to implement an UVM verification environment for an open-source RISC-V processor core. Moreover, the thesis should highlight the main issues and propose solutions to make the process much more efficient in terms of time consuming, memory and resource occupation, and more portable.
This thesis is developed in cooperation with the SYNOPSYS group in Padova; eventually, it would be possible to perform the thesis in the company and receive a cost refund during the thesis period.
Required skills C, Verilog, SystemVerilog
Deadline 31/12/2024
PROPONI LA TUA CANDIDATURA