| KEYWORD |
Definition of a flow to measure the maximum achievable clock frequency of SoC under worst-case conditions
Thesis in external company 
Thesis abroad
keywords TESTING
Reference persons PAOLO BERNARDI
Research Groups GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD
Thesis type RESEARCH / EXPERIMENTAL
Description The performance of an SoC (System on a Chip) is defined as the maximum achievable clock frequency under worst-case conditions. The performance is difficult to measure directly. Therefore, on-chip monitor structures are added to the SoC, which provides an indirect view of performance. The implementation of those on-chip monitor structures should be integrated and established into the industrial SoC design flow. The thesis aims to establish advanced implementation methodologies for the on-chip monitor structures using design-for-test methods. All stages from the concept to the implementation on-chip are covered in the thesis. The student will gain a broad insight into industrial SoC development.
In collaboration with INFINEON, Munich
Required skills Being familiar with digital circuit design
Knowledge about design for test (DFT)
EDA tools (Simulation-Fault simulation) and Python
Deadline 03/07/2021
PROPONI LA TUA CANDIDATURA