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  KEYWORD

Definition of a flow to measure the maximum achievable clock frequency of SoC under worst-case conditions

azienda Tesi esterna in azienda    estero Tesi all'estero


Parole chiave TESTING

Riferimenti PAOLO BERNARDI

Gruppi di ricerca GR-05 - ELECTRONIC CAD & RELIABILITY GROUP - CAD

Tipo tesi RICERCA SPERIMENTALE E TEORICA

Descrizione The performance of an SoC (System on a Chip) is defined as the maximum achievable clock frequency under worst-case conditions. The performance is difficult to measure directly. Therefore, on-chip monitor structures are added to the SoC, which provides an indirect view of performance. The implementation of those on-chip monitor structures should be integrated and established into the industrial SoC design flow. The thesis aims to establish advanced implementation methodologies for the on-chip monitor structures using design-for-test methods. All stages from the concept to the implementation on-chip are covered in the thesis. The student will gain a broad insight into industrial SoC development.
In collaboration with INFINEON, Munich

Conoscenze richieste Being familiar with digital circuit design
Knowledge about design for test (DFT)
EDA tools (Simulation-Fault simulation) and Python


Scadenza validita proposta 03/07/2021      PROPONI LA TUA CANDIDATURA