Memory access optimizations for executing deep neural networks on multi-core microcontrollers
Parole chiave APPRENDIMENTO PROFONDO, BASSO CONSUMO, EFFICIENZA ENERGETICA, INTELLIGENZA ARTIFICIALE, MICROCONTROLLORI, RETI NEURALI CONVOLUZIONALI, RETI NEURALI PROFONDE, SISTEMI EMBEDDED
Riferimenti DANIELE JAHIER PAGLIARI
Riferimenti esterni Alessio Burrello (University of Bologna)
Gruppi di ricerca DAUIN - GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA, ELECTRONIC DESIGN AUTOMATION - EDA, GR-06 - ELECTRONIC DESIGN AUTOMATION - EDA
Tipo tesi SPERIMENTALE, SVILUPPO SW
Descrizione The time and energy costs for accessing data and parameters in memory dominate the total costs of convolutional neural networks inference on general purpose hardware. Therefore, optimizing the arrangement of data, so that the necessary inputs for execution are kept in the lowest-access-cost memory as much as possible is necessary.
The goal of this thesis is the development of an automatic tool to optimize transfers across multiple memory hierarchy levels to minimize the cost of convolutional neural networks inference. Given a network topology, the tool will be able to determine the best layout of weights and data, and the best scheduling of data transfers between levels, in order to minimize inference latency (or energy consumption) on the commercial, ultra-low-power, multi-core platform GAP8.
Conoscenze richieste Required skills include C and Python programming. Furthermore, a basic knowledge of computer architectures and embedded systems is necessary. Desired (but not required) skills include some familiarity with basic machine/deep learning concepts and the corresponding models.
Note Thesis in collaboration with Prof. Luca Beniniís research group at the University of Bologna and ETH Zurich. The thesis can be carried out either in Torino or in one of the other two universities.
Scadenza validita proposta 01/06/2022 PROPONI LA TUA CANDIDATURA